1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device having a wafer-level package structure that makes it possible to execute the CSP (Chip Size Package) process on the wafer.
2. Description of the Related Art
In recent years, development of the LSI technology as the key technology to implement the multimedia equipments is proceeding steadily to the higher speed and the larger capacity of the data transmission. A higher density of the packaging technology as the interface between the LSI and the electronic equipment is also promoted pursuant to this progress.
As the IC package to meet such requirements, there is known the CSP (Chip Size Package) that is packaged in the almost same size as a chip size. In addition, there is known the wafer-level CSP from which individual CSP can be obtained by executing film formation, processing, etc. required for the CSP structure at the wafer stage and then dicing such wafer.
(Related Art 1)
FIGS. 1A to 1H are sectional views showing a bump forming method in the wafer-level CSP according to the related art 1. As shown in FIG. 1A, predetermined elements and multi-layered wirings (not shown) are formed on a semiconductor substrate 100. Then, electrode pads 104 are buried in an interlayer insulating film 102 as the multi-layered wirings. Then, a passivation film 106 is formed on the interlayer insulating film 102 to expose the electrode pads 104.
In the bump forming method in the wafer-level CSP according to the related art 1, as shown in FIG. 1B, first the semiconductor substrate 100 having the passivation structure is prepared. Then, a barrier conductive film 108 used also as a plating-power feeding layer is formed on the passivation film 106 and the electrode pads 104. Then, a first dry-film photoresist 110 is laminated on the barrier conductive film 108.
Then, as shown in FIG. 1C, opening portions 110a are formed on the barrier conductive film 108 in areas containing the electrode pads 104 by exposing/developing the first dry-film photoresist 110.
Then, as shown in FIG. 1D, a gold (Au) film, a copper (Cu) film, or the like is grown in the opening portions 110a of the first dry-film photoresist 110 by the electrolytic plating utilizing the barrier conductive film 108 as the plating-power feeding layer. Thus, metal bumps 112 are formed in the opening portions 110a. 
Then, as shown in FIG. 1E, the first dry-film photoresist 110 is removed. Then, as shown in FIG. 1F, a second dry-film photoresist is laminated on the metal bumps 112 and the barrier conductive film 108, and then exposed/developed. Thus, resist masks 114a for covering upper surfaces and side surfaces of the metal bump 112 respectively are formed.
Then, as shown in FIG. 1G, the exposed barrier conductive film 108 is wet-etched by utilizing the resist masks 114a as a mask. At this time, the barrier conductive film 108 is side-etched into the insides of the resist masks 114a. Thus, barrier film patterns 108a are formed.
Then, as shown in FIG. 1H, the resist masks 114a are removed. Thus, metal bumps 112 that are connected electrically to the electrode pads 104 via the barrier film patterns 108a are formed.
(Relate Art 2)
FIGS. 2A and 2B are sectional views showing a bump forming method in the wafer-level CSP according to the related art 2. In the bump forming method in the wafer-level CSP according to the related art 2, as shown in FIG. 2A, first the semiconductor substrate 100 on which the elements and the multi-layered wirings, etc., which are similar to those in above FIG. 1A, are formed is prepared. Then, as shown in FIG. 2B, stud bumps 112x each having a pointed top end are formed on the electrode pads 104 by the wire bumping method.
In other words, a metal wire made of gold, or the like is pulled out from the capillary of the wire bonder by a predetermined length. Then, the top end portion of this metal wire is rounded like a ball by the electric discharge. Then, the ball-like top end portion of the metal wire is brought into contact with the electrode pad 104 by lowering the capillary. Then, the metal wire is jointed to the electrode pad 104 by applying the heat and the ultrasonic vibration.
Then, the metal wire is pulled off by fixing the metal wire by the clamper while pulling up the capillary. Thus, the stud bumps 112x that are connected electrically to the electrode pad 104 and have the pointed top end are formed.
(Related Art 3)
FIGS. 3A to 3H are sectional views showing a bump forming method in the wafer-level CSP according to the related art 3. In the bump forming method in the wafer-level CSP according to the related art 3, as shown in FIG. 3A, first the semiconductor substrate 100 on which the elements and the multi-layered wirings, etc., which are similar to those in above FIG. 1A, are formed is prepared. Then, as shown in FIG. 3B, the barrier conductive film 108 is formed on the passivation film 106 and the electrode pads 104.
Then, as shown in FIG. 3C, a photosensitive resist film is coated on the barrier conductive film 108, and then is exposed/developed. Thus, resist masks 114a are formed selectively on the barrier conductive film 108 in the areas containing the electrode pads 104.
Then, as shown in FIGS. 3D and 3E, exposed portions of the barrier conductive film 108 are wet-etched by utilizing the resist masks 114a as a mask. Then, the resist masks 114a are removed. Thus, barrier film patterns 108a that are connected electrically to the electrode pads 104 are formed.
Then, as shown in FIG. 3F, solder paste 116 is coated on the barrier film patterns 108a by the screen printing method, or the like. Then, as shown in FIG. 3G, solder balls 112y are put on the solder paste 116, and then reflow-heated. Thus, as shown in FIG. 3H, solder bumps 112z that are connected electrically to the electrode pads 104 via the barrier film patterns 108a are formed.
In the related art, according to the method such as one of the above-described related arts 1 to 3, etc., the metal bumps that are connected electrically to the electrode pads 104 are formed, and then the semiconductor substrate 100 is diced. Thus, the semiconductor devices each having the CSP structure are manufactured.
In the related art 1, when the metal bumps 112 are to be jointed to the connecting pads on the wiring substrate, the top end surfaces, which have a relatively large area, of the metal bumps 112 and the connecting pads are jointed together via the solder paste, or the like. Therefore, an amount of solder that is interposed between the metal bumps 112 and connecting pads is increased indispensably. As a result, there is caused such a problem that a thickness of the electronic parts in which the semiconductor device and the wiring substrate are jointed together is increased.
In addition, when the barrier film patterns 108a are formed by wet-etching the barrier conductive film 108, a depth of side-etching of the barrier conductive film 108 that comes into contact with the metal bump 112 is relatively large. Thus, the metal bumps 112 must be formed larger than the electrode pad 104 by estimating such depth of side-etching. Therefore, the method in the related art 1 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed, and also it is possible that the metal bumps 112 come into contact with each other.
Also, in the related art 2, since the stud bumps 112x are formed by bonding the metal wire with the pressure, the area of the top end surface that is jointed to the connecting pad on the wiring substrate tends to reduce. Thus, there is such a possibility that reliability of the jointing is lowered. Also, since the wire-bonding equipment is used, there is a limit to the pitch between the formed stud bumps 112x and also there is a limit to the reduction in size of the stud bump 112x itself. As a result, the method in the related art 2 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed.
Also, in the related art 3, since the solder balls 112y are employed, it is difficult to reduce the thickness of the electronic parts because of the same reason as the related art 1. Also, when the solder balls 112y are electrically jointed to the barrier conductive film 108 by the reflow-heating, such solder balls 112y are also re-flown in the lateral direction. As a result, the method in the related art 3 cannot easily deal with the case that the pitch between the electrode pads 104 should be narrowed, and also there is such a possibility that the solder bumps 112z come into contact with each other.
In this case, in Patent Application Publication (KOKAI) 2001-57374, the semiconductor device having the conductive bumps that are connected to the bonding pads on the semiconductor substrate is set forth. But no regard is paid to the above-mentioned problems.